Synchronous logic array circuits are well known in the art. Typically, they are known as programmable logic arrays or PLA's. A PLA is typically a logic array circuit comprising two arrays of logic gates: a first array of AND gates and a second array of OR gates. The PLA is adapted to receive a plurality of input signals into the first array. From the first array of AND gates, the output signals are then passed to a buffer, typically called a minterm buffer. From the minterm buffer, the signals are received as input to the second array of OR gates. From the second array of OR gates, the output signal of the second array is passed to an output buffer which provides the output of the PLA.
In a synchronous PLA, the action of inputting the signal into the first array, the output of the signal from the first array into the minterm buffer, the input of the signal from the minterm buffer into the second array, and the output of the signal from the second array into the output buffer are all controlled by a clock signal. Heretofore, in the prior art, a synchronous PLA of the type just described functions by inputting the input signal into the first array upon the falling edge of a clock, and by the input of the input signal from the minterm buffer into the second array upon the rising edge of a clock. Thus, a synchronous PLA of the prior art has required two clock phases: a falling edge clock phase and a rising edge clock.
A further problem with the synchronous PLA of the prior art is that the minterm buffer and the output buffer must switch state for every clock cycle. Therefore, the current must flow from the power lines through each of the transistors in the minterm buffer or the output buffer. Since there are many transistors that switch, the metal power supply line that supplies the power must be wide to accommodate the large current. This has required a wide metal supply line or the pitch of the supply line must be big.
Finally, there are problems with glitches of the synchronous PLA's of the prior art. A glitch is an undesirable dip in the output from the output buffer and the minterm buffer of the synchronous PLA caused by the delayed discharging of the OR array and AND array respectively. Thus, the effect of the synchronous PLA of the prior art is that for both minterm buffers and output buffers, there is higher current, accompanied by increased power consumption, with glitches in the output.
In the prior art, a dummy line for a RAM/ROM array is also known. When a particular word line (a particular row) of a RAM/ROM array is addressed, that word line being activated also activates a transistor in the corresponding row of the dummy line. Thereafter, the signal in the dummy line from that row is propagated along the length or the column of the RAM/ROM array until the signal in the dummy line reaches an output buffer trigger causing it to trigger the output buffer. The signals from the particular word line are propagated along the columns and are gated into the output buffer upon receipt of a signal from the output buffer trigger.